The present invention belongs to the field of electronic component manufacturing processes. It relates more specifically to a method for selecting electronic components, in particular deep submicron semiconductors.
With technological advances in miniaturization and the introduction of new materials, predicting the lifetime and failure rate of deep submicron (DSM) semiconductors has acquired great importance.
Integrated circuit manufacturers manage these problems based on goals of low cost and high performance for the mass market, with a component lifetime criterion of 10 years in use (operating conditions, 0.1% cumulative failures, 90% confidence). This approach does not satisfy the requirements for long-term high reliability and lifetime encountered in professional electronic systems such as aeronautics, space, defense, health, transport, energy or industrial installations.
The following table presents the example of long-term reliability required in the aerospace and energy industries:
Requirements for the equipmentApplicationFailure rateLifetimeSpace satellite10FITs15 yearsCivil avionics100FITs30 yearsNuclear power plant10-100FITs60 years
In most of these applications, these failure rates and lifetime specifications are achieved through redundancy of the printed circuits and equipment.
However, any solution must be based on knowledge of the component's failure rate in relation to the mission's profile and the assurance of a fairly good level of reliability. With this knowledge, the necessary redundancy can be prepared so that a failure rate and lifetime margin can be obtained which respect the specifications of the equipment in question.
Today it is envisaged to use a large range of commercial off-the-shelf (“COTS”) deep-submicron-generation components in their design. The main advantages of these components compared to specific components are their high performance levels and low price, but their reliability in severe environments is still questionable.
Generally, the components' qualification reports and technical data sheets provided by the integrated circuit manufacturers are used to estimate the components' failure rate, in use, based on Accelerated Tests (AT) and Acceleration Factors (AF).
The accelerated tests are carried out at the component level and are generally mentioned in the manufacturer's qualification report.
The activation energy depends on the failure mechanism and the degradation models. The failure mechanism is determined by the technological and design choices. Thus, choosing a small gate length with a SiON gate oxide will favor a charge injection mechanism in the gate. Taking a default activation energy can result in a greatly distorted estimate of the component's reliability. For example, an overestimated activation energy in an acceleration factor leads to an underestimation of the failure rate in use.
Integrated circuit manufacturers rarely take into account environmental conditions, long-term use and other parameters linked to professional electronics, because these parameters do not concern products intended for the mass market. In these severe conditions, a factor of 4 can even be obtained for commercial off-the-shelf (“COTS”) components (FIG. 1 and FIG. 2).
As a result, knowledge of acceleration factor models and parameters based on the technology is essential for estimating reliability.
Unfortunately, professional electronics are only a very small market for circuits with very large-scale integration (“VLSI”) and information is not available for these markets. To overcome this problem a dedicated reliability analysis at the silicon level must be performed for each electronic component in order to collect basic information and build a reliability prediction.
An initial step of the method consists of gathering basic information about the component: manufacturer, foundry and if possible data relating to the manufacturing process and the technology.
When the required information is not available in the literature, the component is studied using a process of reverse engineering at the silicon level.
The research is carried out to draw up the component's identity card with regard to the final foundry steps (“Back End Of Line”—BEOL) and initial foundry steps (“Front End Of Line”—FEOL), where at least the following information is extracted:                The technological generation or node (half-step parameter),        Number of metal layers, materials and dimensions of the metallization and interconnections,        Transistor material and dimensions,        Substrate type (Silicon on insulator or “massive bulk” silicon).        
A next step consists of analyzing the component's sensitivity relative to its mission profile, such as the examples of aeronautics mission profiles illustrated in the following table.
ProfileUseexampleStorageApplication110% operating cycle90% operating cycle25° C.25/70° C., VDDno polarizationno assembly299% operating cycle1% operating cycle25° C.−55/125° C., VDDno polarizationassembled
These profiles must be taken into account when estimating reliability.
For example, compared to operational situations the emergence of failure mechanisms activated by the voltage, such as electromigration and the burnout of the gate oxide, are unlikely in non-powered storage conditions.
Regardless of the mission profile, some materials and architectures are known to be more sensitive to certain mechanisms. For example, the porosity of low-k oxide makes it easier for the oxide of the inter-layer dielectric (ILD) to fail. In addition, during the BEOL step there are large variances between the thermal expansion coefficients of the copper in double damascening, of the diffusion layer and of the dielectric oxides of the intermediate layer, which makes the technology more sensitive to damage by migration under constraints.
In Silicon On Insulator (SOI) technology, the insulator layer prevents dissipation by Joule effect to spread through the substrate, which induces a thermal acceleration of the silicon's failure mechanisms.
On the other hand, for the same gate length the consumption of dynamic power is lower in SOI technology than in bulk substrates, which offsets these thermal weaknesses.
Finally, gate oxides with high permittivity values seem to be more sensitive to the instability mechanisms of the threshold voltage in temperature than the traditional SiON oxide, due to a greater physical thickness, a larger number of interfaces and the initial presence of mobile charges in the oxide.
The sensitivity analysis provides an indication of the silicon's failure mechanisms that are the most likely to occur.
By elimination the predominant mechanisms to be studied are selected, as well as the qualification report tests that must be the subject of a subsequent analysis.
The predominant failure mechanisms of the circuits also provide information about the time dependency of the failure. Some of these are typical of the bottom of the reliability bath curve and some others are defined as wear-out mechanisms (FIG. 3).
In the first case, the reliability is best described by a constant instantaneous failure rate (designated by A and expressed in FITs—“Failure in Time”), whereas for the mechanism of failure by wear-out, it is the lifetime that is talked of instead: “Time to Failure” (TTF) in hours, the time at which the probability of failure F(t) reaches the specified value, e.g. 10−7 or 10−9 for some aeronautical applications.
Manufacturers of integrated circuits generally deduce an instantaneous failure rate from a high-temperature operating life (HTOL) test through the χ2 estimator.
The main advantage of this estimator is to extrapolate a failure rate from a small sample to a large quantity of components with a known confidence coefficient (FIG. 4). This method is still acceptable for the failure mechanism occurring when the failure rate is constant and independent of the duration of the test.
However, this calculation is no longer suitable for wear mechanisms, simply because the failure rate increases with time.